library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cnt60_min is
	port(clk_min:in std_logic;--clock signal(carry signal from cnt60_sec.vhd)
		set_min:in std_logic;--set time enable
		clr:in std_logic;--clear
		qin_min:in std_logic_vector(7 downto 0);--8421 code from set entity
		qout_min:out std_logic_vector(7 downto 0);--output 8421 code
		carry_min:out std_logic;--carry bit for hour
		);
end cnt60_min;

architecture func of cnt60_min is
	signal temp1:std_logic_vector(3 downto 0);--right digit
	signal temp10:std_logic_vector(3 downto 0);--left digit
begin
		process(set_min,clk_min,clr)
		begin
			if(clr='1') then
				temp1<="0000";
				temp10<="0000";
				carry_min<='0';
			elsif(set_min='1') then
				temp10<=qin_min(7 downto 4);
				temp1<=qin_min(3 downto 0);
				carry_min<='0';
			elsif(clk_min'event and clk_min='1') then
				if(temp1=9) then
					temp1<="0000";
					if(temp10=5) then
						temp10="0000";
						carry_min<='1';
					else
						temp10<=temp10+1;
						carry_min<='0';
					end if;
				else
					temp1<=temp1+1;
					carry_min<='0';
			end if;
			qout_min<=temp10 & temp1;
		end process;
end func;